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Integrated Circuit Systems, Inc.
ICS960002
Power PC Based LBP
Features - CPU, ASIC, and PCI can run at 2.5V or 3.3V selectable. - Generates the following system clocks: 1-CPU (2.5V/3.3V) (66.66MHz to 100.00MHz) 2-PCI (2.5V/3.3V) (33.33MHz) 2-ASIC (2.5V/3.3V) (66.66MHz to 100.00MHz) 1-ASIC (2.5V/3.3V) (33.33MHz to 100.00MHz) 1-USB (3.3V) (48MHz) - SKEW Characteristics: CPU to ASIC < 250ps - Jitter Characteristics CPU/ASIC <150ps (cycle to cycle) -Spread Spectrum features Off -0.5%, 1.0%, and 1.25% Downspread - Power Management Enable/Disable PCI, ASIC2, and/or USB independently - Uses external 14.318MHz crystal or reference clock
Pin Configuration
GNDCOR SSC1/ASIC_3.3V_2.5# SSC0/CPU_3.3V_2.5# X1 X2 VDDCOR VDDDIG VDDPCI PCICLK0/PCI_3.3V_2.5# PCICLK1/PCI_EN* GND GND USB0/USB_EN* VDDUSB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 GND CPUCLK0 VDDCPU VDDASIC2 ASIC2A/ASIC2A_EN* ASIC2B GND GND ASIC1 VDDASIC1 GND ASIC1_SEL* CLK_SEL1 CLK_SEL0
Note: * 60Kohm to 120Kohm Internal Pullup Resistor
209Mil SSOP
Block Diagram
VDDCOR, DIG, USB=3.3V 3 XIN XOUT XTAL OSC VDDCPU, ASIC1, ASIC2, PCI = 2.5V or3.3V 4
Power Groups
Pin Number VDD GND
USB
ICS60002
Description
PLL2
STOP
CPU Divider PLL1 Spread Spectrum DIV 2 STOP
CPU
ASIC1
ASIC2A
6, 7 8 14 19 25 26
1, 18 11 12 21 22 28
3.3V Internal Logic and Core Power PCI outputs USB outputs ASIC1 outputs ASIC2 outputs CPU ouputs
SSC [1:0] USB_EN CLK_SEL [1:0] PCI_EN ASIC2A_EN ASIC_SEL
Control Logic Configuration Resistor PCI Divider
ASIC2B
PCI (1:0) 2
3 GNDCOR, DIG, USB=0V
4 GNDCPU, ASIC1, ASIC2, PCI = 0V
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Pentium is a trademark of Intel Corporation.
ICS960002
Pin Descriptions
PIN # PIN NAME PIN TYPE DESCRIPTION
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
GNDCOR SSC1/ASIC_3.3V_2.5# SSC0/CPU_3.3V_2.5# X1 X2 VDDCOR VDDDIG VDDPCI PCICLK0/PCI_3.3V_2.5# PCICLK1/PCI_EN* GND GND USB0/USB_EN* VDDUSB CLK_SEL0 CLK_SEL1 ASIC1_SEL* GND VDDASIC1 ASIC1 GND GND ASIC2B ASIC2A/ASIC2A_EN* VDDASIC2 VDDCPU CPUCLK0 GND
PWR IN IN IN OUT PWR PWR PWR I/O I/O PWR PWR I/O PWR IN IN IN PWR PWR OUT PWR PWR OUT I/O PWR PWR OUT PWR
Ground pin for the PLL core. Spread Spectrum amplitude control with latched VDDASIC 3.3V/2.5V# select. Spread Spectrum amplitude control with latched VDDCPU 3.3V/2.5V# select. Crystal input,nominally 14.318MHz. Crystal output, Nominally 14.318MHz 3.3V power for the PLL core. 3.3V internal digital power. Power supply for PCI clocks, nominal 3.3V PCI clock output with latched VDDCPU 3.3V/2.5V# select. PCI clock output with latched PCI enable function at startup. Ground pin. Ground pin. USB clock output with latched USB enable function at startup. Supply for USB clocks,3.3V nominal Function select pin. See table for details. Function select pin. See table for details. Function select pin. See table for details. Ground pin. Supply for ASIC1clocks,3.3V nominal ASIC1 clock output. Ground pin. Ground pin. ASIC2B clock output. ASIC2A clock output with latched ASIC2A_EN enable function at startup. Supply for ASIC2 clocks,3.3V nominal Supply for CPU clocks, 3.3V nominal CPU clock outputs. 3.3V Ground pin.
NOTE: Internal pull-up resitors on pin 10, 13, 17, and 24. No internal resistor for pin 2, 3, 9, 15 or 16. Pin 2, 3 and 9 functionality: When the device Powers-up, the pin work as latch pin to decide supply voltage on VDDxxx, and then will work as select pin of SS(or output pin). When High(VDD=3.3V) is latched, the output buffer of xxx will be optimized at VDDxxx=3.3V, When Low(GND) is latched, the output buffer of xxx will be optimized at VDDxxx=2.5V. The voltage of the latch point is approximate VDDCORE/DIG=1.8V. and it will take effect within the time of clock stabilization.
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ICS960002
Frequency Tables
CLK_SEL1 0 0 1 1 CLK_SEL0 0 1 0 1 CPU (MHz) 66.66 100.00 83.33 88.88 ASIC1 (MHz) ASIC2 [A, B] ASIC1_SEL=1 ASIC1_SEL=0 (MHz) 66.66 33.33 66.66 100.00 50.00 100.00 83.33 41.67 83.33 88.88 44.44 88.88
Spread Spectrum Selection Table
SSC1 0 0 1 1 SSC0 0 1 0 1 Spread Spectrum Modulation [MHz] OFF -0.50% Down Spread -1.00% Down Spread -1.25% Down Spread
Power Management Table
USB_EN 0 1
X X X X
PCI_EN
X X
ASIC2_EN
X X
USB Tri-state 48MHz
X X X X
PCICLK(1,0)
X X
ASIC2A X X
X X
0 1
X X
X X
0 1
Tri-state 33.3MHz
X X
Tri-state SELECTED
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ICS960002
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 5.5V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . 0C to +70C Storage Temperature . . . . . . . . . . . . . . . . . . . -65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - AC Specification
TA = 0 - 70C; VDD = 3.3 V or 2.5V +/-5%; CL=20pF(unless otherwise stated) PARAMETERS SYMBOL CONDITIONS MIN. 12 Input Frequency ZO SST modulation sweep rate fmod Transition Time Settling Time TTrans TS CIN COUT CINX tr2B tf2B dt2B tsk2B tjitabs2B tjitabs2B tjitabs2B tjcyc-cyc2B tjcyc-cyc2B tjcyc-cyc2B To 1st crossing of target Freq. From 1st crossing to 1% target Freq. Logic Inputs Output pin capacitance X1 & X2 pins 0.8V to 2.0V with no load 2.0V to 0.8V with no load At VDD/2 Equal Power Supply for both ASIC and CPU at same Frequency; Cl =20 pF CPU and ASIC only. PCI USB CPU and ASIC only. PCI USB TYP. 14.31818 32.2 1.1 1.5 <2 <2 30 MAX. UNITS 16 MHz kHz 3 3 5 6 45 1.5 1.5 55 250 150 175 150 120 200 150 ms ms pF pF pF ns ns % ps ps
Input Capacitance Output Rise Time Output Fall Time Duty Cycle CPU and ASIC Skew
27
0.5 0.5
45 50 200
Max. Absolute Period Jitter
-150 -175 -150
90
Max. Jitter, cycle to cycle
110 95
ps ps ps
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ICS960002
Electrical Characteristics - DC Specification
TA = 0 - 70C; VDD =See table below; CL = 20 pF (unless otherwise stated) PARAMETERS SYMBOL CONDITIONS MIN. VDDCOR Nominal voltage is 2.97 VDDDIG 3.3V VDDUSB Operating Voltage VDDPCI 2.25 Nominal voltage is VDDASIC1 3.3V or 2.5V VDDASIC2 2.97 VDDCPU For all normal input 2 Input High Voltage VIH For all normal input VSS - 0.3 Input Low Voltage V IL IOH = -25mA 2.4 Output High Voltage VOH3.3 IOL = 25mA Output Low Voltage VOL3.3 IOH = -25mA 2 Output High Voltage VOH2.5 IOL = 25mA Output Low Voltage VOL2.5 Operating Supply No Load IDD Current TYP. MAX. 3.63 2.75 3.63 VDD + 0.3 0.8 0.4 0.4 35 UNITS V V V V V V V V V mA
3.3V 2.5V 3.3V
50
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ICS960002
Shared Pin Operation Input/Output Pins
The I/O pins designated by (input/output) serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used both to provide the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. When no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, then only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor.
Programming Header Via to Gnd Device Pad 2K W
Via to VDD
8.2K W Clock trace to load Series Term. Res.
Fig. 1
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ICS960002
N
c
L
INDEX AREA
E1
E
12 D
A2 A1
A
209 mil SSOP In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A -2.00 -.079 A1 0.05 -.002 -A2 1.65 1.85 .065 .073 b 0.22 0.38 .009 .015 c 0.09 0.25 .0035 .010 SEE VARIATIONS SEE VARIATIONS D E 7.40 8.20 .291 .323 E1 5.00 5.60 .197 .220 0.65 BASIC 0.0256 BASIC e L 0.55 0.95 .022 .037 SEE VARIATIONS SEE VARIATIONS N 0 8 0 8 VARIATIONS N 28
1 0-0033
-Ce
b SEATING PLANE .10 (.004) C
D mm. MIN 9.90 MAX 10.50 MIN .390
D (inch) MAX .413
Reference Do c.: JEDEC P ublicatio n 95, M O-1 50
209 mil SSOP
Ordering Information
ICS960002yF-T
Example:
ICS XXXX y F - T
Designation for tape and reel packaging Package Type F=SSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device
0677E--03/05/03
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